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iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 iso742x low-power dual-channel digital isolators 1 features 3 description the iso7420, ISO7420M and iso7421 provide 1 ? highest signaling rate: 1 mbps galvanic isolation up to 2500 v rms for 1 minute per ? low power consumption, typical i cc per channel ul. these digital isolators have two isolated (3.3-v operation): channels. each isolation channel has a logic input ? iso7420: 1.1 ma, iso7421: 1.5 ma and output buffer separated by a silicon dioxide (sio 2 ) insulation barrier. used in conjunction with ? low propagation delay ? 9 ns typical isolated power supplies, these devices prevent noise ? low skew ? 300 ps typical currents on a data bus or other circuit from entering ? wide t a range: ? 40 c to 125 c (m-grade) the local ground and interfering with or damaging sensitive circuitry. the suffix m indicates wide ? 50-kv/ s transient immunity, typical temperature range ( ? 40 c to 125 c). ? over 25-year isolation integrity at rated voltage these devices have ttl input thresholds and require ? operates from 3.3-v and 5-v supply and logic two supply voltages, 3.3 or 5 v, or any combination. levels all inputs are 5-v tolerant when supplied from a 3.3-v ? 3.3-v and 5-v level translation supply. ? narrow body soic-8 package note: the iso7420 and iso7421 are specified for ? safety and regulatory approvals: signaling rates up to 1 mbps. due to their fast ? 4242 v pk isolation per din v vde v 0884-10 response time, under most cases, these devices will and din en 61010-1 also transmit data with much shorter pulse widths. designers should add external filtering to remove ? 2500 v rms isolation for 1 minute per ul 1577 spurious signals with input pulse duration < 20 ns if ? csa component acceptance notice 5a, iec desired. 60950-1 and iec 61010-1 standards device information (1) ? cqc certification per gb4943.1-2011 part number package body size (nom) 2 applications iso7420 ISO7420M soic (8) 4.90 mm 3.91 mm ? optocoupler replacement in: iso7421 ? industrial fieldbus (1) for all available packages, see the orderable addendum at ? profibus the end of the data sheet. ? modbus ? devicenet ? data buses ? servo control interface ? motor control ? power supplies ? battery packs simplified schematic v cci and gndi are supply and ground connections respectively for the input channels. v cco and gndo are supply and ground connections respectively for the output channels. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. unless otherwise noted, this document contains production data. outx gndo gndi inx v cco v cci isolation capacitor productfolder sample &buy technical documents tools & software support &community
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com table of contents 5% .......................................................................... 11 1 features .................................................................. 1 6.14 typical characteristics .......................................... 12 2 applications ........................................................... 1 7 parameter measurement information ................ 13 3 description ............................................................. 1 8 detailed description ............................................ 14 4 revision history ..................................................... 2 8.1 overview ................................................................. 14 5 pin configuration and functions ......................... 6 8.2 functional block diagram ....................................... 14 6 specifications ......................................................... 7 8.3 feature description ................................................. 15 6.1 absolute maximum ratings ..................................... 7 8.4 device functional modes ........................................ 17 6.2 esd ratings .............................................................. 7 9 application and implementation ........................ 18 6.3 recommended operating conditions ....................... 7 9.1 application information ............................................ 18 6.4 thermal information .................................................. 8 9.2 typical application ................................................. 18 6.5 electrical characteristics: v cc1 and v cc2 at 5 v 5% ............................................................................ 8 10 power supply recommendations ..................... 20 6.6 electrical characteristics: v cc1 at 5 v 5%, v cc2 at 11 layout ................................................................... 20 3.3 v 5% .................................................................. 9 11.1 layout guidelines ................................................. 20 6.7 electrical characteristics: v cc1 at 3.3 v 5%, v cc2 at 11.2 layout example .................................................... 20 5 v 5% ..................................................................... 9 12 device and documentation support ................. 21 6.8 electrical characteristics: v cc1 and v cc2 at 3.3 v 12.1 documentation support ........................................ 21 5% .......................................................................... 10 12.2 related links ........................................................ 21 6.9 power dissipation characteristics .......................... 10 12.3 community resources .......................................... 21 6.10 switching characteristics: v cc1 and v cc2 at 5 v 12.4 trademarks ........................................................... 21 5% .......................................................................... 10 12.5 electrostatic discharge caution ............................ 21 6.11 switching characteristics: v cc1 at 5 v 5%, v cc2 at 3.3 v 5% ................................................................ 10 12.6 glossary ................................................................ 21 6.12 switching characteristics: v cc1 at 3.3 v 5%, v cc2 13 mechanical, packaging, and orderable at 5 v 5% ............................................................... 11 information ........................................................... 21 6.13 switching characteristics: v cc1 and v cc2 at 3.3 v 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision h (may 2013) to revision i page ? vde standard changed to din v vde v 0884-10 (vde v 0884-10):2006-12 ...................................................................... 1 ? added pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 changes from revision g (may 2013) to revision h page ? changed feature from: 4~242 vpeak isolation to: 4242 vpeak isolation ........................................................................... 1 changes from revision f (january 2013) to revision g page ? changed v iorm in the insulation characteristics table, specification value from: 56~6 to: 566 ........................ 15 ? changed v pr in the specification value from: 10~62 to: 1062 .......................................................................................... 15 ? changed v iotm t = 60 s (qualification) specification value from: 4~242 to: 4242 .............................................................. 15 changes from revision e (june 2011) to revision f page ? changed feature from: 242 vpeak maximum isolation-per din en 60747-5-2 (vde 0884 part 2) - to: 4~242 vpeak isolation ....................................................................................................................................................................... 1 ? changed feature from: iec/vde and csa approvals, iec 60950-1 ? iec 61010-1 end equipment standards approvals, all approvals pending to: csa 60950-1 and iec 61010-1 approved ................................................................ 1 2 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 ? added table note to v iorm .................................................................................................................................................... 15 ? changed v iorm in the insulation characteristics table, specification value from: 56~0 to: 56~6 ...................... 15 ? changed v pr in the specification value from: 10~50 to: 10~62 ........................................................................................ 15 ? changed v iotm t = 60 s (qualification) specification value from: 4~000 to: 4~242 ............................................................ 15 ? changed the iec 60664-1 ratings table. row - basic isolation group specification from: iii-a to: ii................. 15 ? changed cti in the package characteristics table, min value from: > 175 to 400 .............................................. 15 ? changed the text of note: ................................................................................................................................................. 16 ? changed the regulatory information table ............................................................................................................ 17 changes from revision d (july 2010) to revision e page ? added new fifth bullet to features and deleted text from 4-kvpeak bullet item ..................................................................... 1 ? changed first paragraph in description from: ISO7420M, iso7421, and iso7421m to: ISO7420M and iso7421 .............. 1 ? changed iso742xm in the elec char and switching char table to ISO7420M ........................................................ 8 ? changed iso742xm in the elec char and switching char table to ISO7420M ........................................................ 9 ? changed iso742xm in the elec char and switching char table to ISO7420M ........................................................ 9 ? changed iso742xm in the elec char and switching char table to ISO7420M ...................................................... 10 ? changed the max value in the switching char table 2nd row from 3.5 to 3.7 and 3rd row from 4 to 4.9 ................... 10 ? changed the max value in the 2nd switching char table 2nd row from 4 to 5.6 and 3rd row from 5 to 6.3 ............... 10 ? changed the max value in the 3rd switching char table 3rd row from 5 to 8.5 ......................................................... 11 ? changed the max value in the 4rd switching char table 3rd row from 6 to 6.8 ......................................................... 11 ? changed regulatory information table last row, last column from: pending (e181974) to: e181974 ................................. 17 ? changed note 2 in function table from: ISO7420M, iso7421, and iso7421m to: ISO7420M and iso7421 ................... 17 changes from revision c (march 2010) to revision d page ? updated the features list ...................................................................................................................................................... 1 ? deleted devices iso7420f and iso7420fm from the data sheet ......................................................................................... 1 ? updated the device description. add paragraph - note: the iso7420 and iso7421 ........................................................... 1 ? added tstg to the absolute maximum ratings table ............................................................................................................ 7 ? updated the recommended operating conditions table ....................................................................................................... 7 ? updates throughout the electrical characteristics and switching characteristics tables ...................................................... 8 ? updated the supply current test conditions ........................................................................................................................... 8 ? deleted the supply current vs signal rate (all channels) graphs and the eye diagram plots ................. 12 ? changed figure 7 ................................................................................................................................................................. 13 ? changed the v iorm , v pr , and v iotm unit values from: v to: vpeak .................................................................................... 15 ? changed minimum internal gap min value from: 0.008 to: 0.014mm ............................................................................... 15 ? changed the barrier capacitance, input to output test conditions ........................................................................................ 15 ? changed the input capacitance test conditions ................................................................................................................... 15 ? changed v i from: 5.5 v to: 5.25 v ..................................................................................................................................... 16 ? changed from: 107ma to: 112ma...................................................................................................................................... 16 ? changed v i from: 3.6 v to: 3.45 v ..................................................................................................................................... 16 ? changed from: 164ma to: 171ma...................................................................................................................................... 16 ? changed figure 10 ............................................................................................................................................................... 16 ? deleted the i cc equations section ......................................................................................................................................... 16 ? changed the function table output values for pu (open) from: h/l to: h ...................................................................... 17 ? changed figure 11 ............................................................................................................................................................... 17 copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com changes from revision b (february 2010) to revision c page ? added devices iso7420f and iso7420fm to the data sheet ............................................................................................... 1 ? added the suffix m indicates wide temperature range ( ? 55 c to 125 c) and the suffix f indicates output-low option in fail-safe condition. all other devices without the f suffix default to output-high in fail-safe state. ..................................... 1 ? added iso7420f and iso7420fm to the available options table ....................................................................................... 6 ? changed value from a max of 4 ma to a min of ? 4 ma ......................................................................................................... 7 ? changed value from a min of ? 4 ma to a max of 4 ma ........................................................................................................ 7 ? changed electrical characteristics conditions ....................................................................................................................... 8 ? deleted c i from the electrical characteristics ....................................................................................................... 8 ? added (all inputs switching with square wave clock signal for dynamic icc measurement) ................................................. 8 ? changed electrical characteristics conditions ...................................................................................................... 9 ? added high-level output voltage iso7420 / 7421 (3.3-v side) test condition ....................................................................... 9 ? changed high-level output voltage min value ........................................................................................................................ 9 ? deleted c i specification .......................................................................................................................................................... 9 ? added (all inputs switching with square wave clock signal for dynamic icc measurement) ................................................. 9 ? changed electrical characteristics conditions ...................................................................................................... 9 ? added high-level output voltage iso7420 / 7421 (5-v side) test condition ........................................................................... 9 ? changed high-level output voltage min value ........................................................................................................................ 9 ? deleted c i specification .......................................................................................................................................................... 9 ? added (all inputs switching with square wave clock signal for dynamic icc measurement) ................................................. 9 ? changed electrical characteristics conditions .................................................................................................... 10 ? deleted c i specification ........................................................................................................................................................ 10 ? added (all inputs switching with square wave clock signal for dynamic icc measurement) ............................................... 10 ? changed switching characteristics conditions ..................................................................................................... 10 ? changed pwd parameter from duration to width ................................................................................................................ 10 ? changed switching characteristics conditions ..................................................................................................................... 10 ? changed pulse duration distortion to pulse width distortion ............................................................................................... 10 ? changed switching characteristics conditions ..................................................................................................................... 11 ? changed switching characteristics conditions ..................................................................................................... 11 ? changed pulse duration distortion to pulse width distortion ............................................................................................... 11 ? changed switching characteristics conditions ..................................................................................................... 11 ? changed pulse duration distortion to pulse width distortion ................................................................................................ 11 ? changed figure 7 ................................................................................................................................................................. 13 ? added input to output and note 1 to isolation resistance, input to output ............................................................................ 15 ? changed the isolation resistance test conditions ................................................................................................................. 15 ? changed the isolation resistance test conditions ................................................................................................................. 15 ? added note 1 to barrier capacitance, input to output ........................................................................................................... 15 ? added input capacitance ...................................................................................................................................................... 15 ? changed t j = 170 c to t j = 150 c ...................................................................................................................................... 16 ? changed from: 124ma to: 107ma...................................................................................................................................... 16 ? changed t j = 170 c to t j = 150 c ...................................................................................................................................... 16 ? changed from: 190ma to: 164ma...................................................................................................................................... 16 ? changed figure 10 ............................................................................................................................................................... 16 ? changed the function table output values for pu (open) from: h to: h/l ...................................................................... 17 ? changed the function table output values for pu (x) from: h to: h/l............................................................................. 17 ? changed the function table output values for pu (x) from: h/l to: h............................................................................. 17 4 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 ? added note (2) in the function table .................................................................................................................................. 17 ? changed figure 11 ............................................................................................................................................................... 17 changes from revision a (december 2009) to revision b page ? switching characteristics table, added note (2) - typical specifications are measured at ideal conditions of 25 c. max or min specifications are measured at worst case conditions for v cc and temperature. ............................................... 8 changes from original (june 2009) to revision a page ? added devices iso7420 and ISO7420M to the data sheet ................................................................................................... 1 ? added the i cc equations section ........................................................................................................................................... 16 copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 5 pin configuration and functions iso7420: d package iso7421: d package 8-pin soic 8-pin soic (top view) (top view) pin functions pin i/o description name iso7420 iso7421 gnd1 4 4 ? ground connection for v cc1 gnd2 5 5 ? ground connection for v cc2 ina 2 7 i input, channel a inb 3 3 i input, channel b outa 7 2 o output, channel a outb 6 6 o output, channel b v cc1 1 1 ? power supply, v cc1 v cc2 8 8 ? power supply, v cc2 6 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421 v cc1 outa inb gnd1 v cc2 ina outb gnd2 12 3 4 8 7 6 5 isolation v cc1 ina inb gnd1 v cc2 outa outb gnd2 12 3 4 8 7 6 5 isolation
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 6 specifications 6.1 absolute maximum ratings see (1) min max unit v cc supply voltage (2) , v cc1 , v cc2 ? 0.5 6 v v i voltage at in, out ? 0.5 v cc + 0.5 (3) v i o output current ? 15 15 ma t j(max) maximum junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to network ground terminal and are peak voltage values. (3) maximum voltage must not exceed 6 v. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001 (1) 4000 field-induced charged-device model, jedec standard 22, test method 1500 v (esd) electrostatic discharge v c101 machine model, ansi/esds5.2-1996 200 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions min nom max unit supply voltage - 3.3-v operation 3.15 3.3 3.45 v cc1 , v v cc2 supply voltage - 5-v operation 4.75 5 5.25 i oh high-level output current ? 4 ma i ol low-level output current 4 ma v ih high-level input voltage 2 5.25 v v il low-level input voltage 0 0.8 v 1/t ui signaling rate 0 1 mbps t ui input pulse duration 1 us t j (1) junction temperature ? 40 136 c iso7420, iso7421 -40 25 105 t a ambient temperature c ISO7420M -40 25 125 (1) to maintain the recommended operating conditions for t j , see the thermal information . copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 6.4 thermal information iso742x thermal metric (1) d (soic) unit 8 pins low-k board 212 r ja junction-to-ambient thermal resistance c/w high-k board 116.6 r jc(top) junction-to-case (top) thermal resistance 71.6 c/w r jb junction-to-board thermal resistance 57.3 c/w jt junction-to-top characterization parameter 28.3 c/w jb junction-to-board characterization parameter 56.8 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics: v cc1 and v cc2 at 5 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit i oh = ? 4 ma; see figure 6 . v cco (1) ? 0.8 4.6 v oh high-level output voltage v i oh = ? 20 a; see figure 6 . v cco ? 0.1 5 i ol = 4 ma; see figure 6 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 6 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 8 . 25 50 kv/ s supply current (all inputs switching with square wave clock signal for dynamic icc measurement) iso7420 i cc1 supply current for v cc1 0.4 1 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 3 6 iso7421 i cc1 supply current for v cc1 2 4 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 2 4 (1) v cci = input-side power supply, v cco = output-side power supply 8 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 6.6 electrical characteristics: v cc1 at 5 v 5%, v cc2 at 3.3 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit i oh = ? 4 ma; iso7421 (5-v side) v cco (1) ? 4.6 see figure 6 . 0.8 v oh high-level output voltage v iso7420 / 7421 (3.3-v side) . v cco ? 0.4 3 i oh = ? 20 a; see figure 6 , v cco ? 0.1 v cc i ol = 4 ma; see figure 6 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 6 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 8 . 25 40 kv/ s supply current (all inputs switching with square wave clock signal for dynamic icc measurement) iso7420 i cc1 supply current for v cc1 0.4 1 ma dc to 1 mbps v i = v cci or 0 v, 15 pf load i cc2 supply current for v cc2 2 4.5 ma iso7421 i cc1 supply current for v cc1 2 4 ma dc to 1 mbps v i = v cci or 0 v, 15 pf load i cc2 supply current for v cc2 1.5 3.5 ma (1) v cci = input-side power supply, v cco = output-side power supply 6.7 electrical characteristics: v cc1 at 3.3 v 5%, v cc2 at 5 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit i oh = ? 4 ma; v cco (1) ? iso7420 / 7421 (5-v side). 4.6 see figure 6 . 0.8 v oh high-level output voltage v iso7421 (3.3-v side) v cco ? 0.4 3 i oh = ? 20 a; see figure 6 v cco ? 0.1 v cc i ol = 4 ma; see figure 6 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 6 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a cmti common-mode transient immunity v i = v cci or 0 v; see figure 8 . 25 40 kv/ s supply current (all inputs switching with square wave clock signal for dynamic icc measurement) iso7420 i cc1 supply current for v cc1 0.2 0.7 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 3 6 iso7421 i cc1 supply current for v cc1 1.5 3.5 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 2 4 (1) v cci = input-side power supply, v cco = output-side power supply copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 6.8 electrical characteristics: v cc1 and v cc2 at 3.3 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit i oh = ? 4 ma; see figure 6 . v cco (1) ? 0.4 3 v oh high-level output voltage v i oh = ? 20 a; see figure 6 . v cco ? 0.1 3.3 i ol = 4 ma; see figure 6 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 6 . 0 0.1 v i(hys) input threshold voltage hysteresis 400 mv i ih high-level input current 10 a inx at 0 v or v cci (1) i il low-level input current ? 10 a common-mode transient cmti v i = v cci or 0 v; see figure 8 . 25 40 kv/ s immunity supply current (all inputs switching with square wave clock signal for dynamic icc measurement) iso7420 i cc1 supply current for v cc1 0.2 0.7 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 2 4.5 iso7421 i cc1 supply current for v cc1 1.5 3.5 dc to 1 mbps v i = v cci or 0 v, 15 pf load ma i cc2 supply current for v cc2 1.5 3.5 (1) v cci = input-side power supply, v cco = output-side power supply 6.9 power dissipation characteristics iso742x thermal metric d (soic) unit 8 pins v cc1 = v cc2 = 5.25 v, t j = 150 c, c l = 15 pf p d device power dissipation 55 mw input a 1-mbps 50% duty-cycle square wave 6.10 switching characteristics: v cc1 and v cc2 at 5 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 6 . 9 14 ns pwd (1) pulse width distortion |t phl ? t plh | 0.3 3.7 ns t sk(pp) part-to-part skew time 4.9 ns t sk(o) channel-to-channel output skew time 3.6 ns t r output signal rise time see figure 6 . 1 ns t f output signal fall time 1 ns t fs fail-safe output delay time from input power loss see figure 7 . 6 s (1) also known as pulse skew. 6.11 switching characteristics: v cc1 at 5 v 5%, v cc2 at 3.3 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 6 . 10 17 ns pwd (1) pulse width distortion |t phl ? t plh | 0.5 5.6 ns t sk(pp) part-to-part skew time 6.3 ns t sk(o) channel-to-channel output skew time 4 ns t r output signal rise time see figure 6 . 2 ns (1) also known as pulse skew. 10 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 switching characteristics: v cc1 at 5 v 5%, v cc2 at 3.3 v 5% (continued) t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit t f output signal fall time 2 ns t fs fail-safe output delay time from input power loss see figure 7 . 6 s 6.12 switching characteristics: v cc1 at 3.3 v 5%, v cc2 at 5 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 6 . 10 17 ns pwd (1) pulse width distortion |t phl ? t plh | 0.5 4 ns t sk(pp) part-to-part skew time 8.5 ns t sk(o) channel-to-channel output skew time 4 ns t r output signal rise time see figure 6 . 2 ns t f output signal fall time 2 ns t fs fail-safe output delay time from input power loss see figure 7 . 6 s (1) also known as pulse skew. 6.13 switching characteristics: v cc1 and v cc2 at 3.3 v 5% t a = ? 40 c to 125 c for ISO7420M, t a = ? 40 c to 105 c for iso742x parameter test conditions min typ max unit t plh , t phl propagation delay time 12 20 ns pwd (1) pulse width distortion |t phl ? t plh | see figure 6 . 1 5 ns t sk(pp) part-to-part skew time 6.8 ns t sk(o) channel-to-channel output skew time 5.5 ns t r output signal rise time 2 ns see figure 6 . t f output signal fall time 2 ns t fs fail-safe output delay time from input power loss see figure 7 . 6 s (1) also known as pulse skew. copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 6.14 typical characteristics figure 1. propagation delay time vs free-air temperature figure 2. input voltage switching threshold vs free-air temperature figure 3. fail-safe voltage threshold vs free-air figure 4. high-level output current vs high-level output temperature voltage figure 5. low-level output current vs low-level output voltage 12 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421 v ol ? low-level output voltage ? v 0 10 20 30 40 50 60 70 80 0 1 2 3 4 5 6 i ol ? low-level output current ? ma v cc1 , v cc2 at 3.3 v g008 v cc1 , v cc2 at 5 v t a = 25c t a ? free-air temperature ? c 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 2.61 2.62 ?55 ?35 ?15 5 25 45 65 85 105 125 fail-safe v oltage threshold ? v g006 fs+ fs? v oh ? high-level output voltage ? v ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 i oh ? high-level output current ? ma v cc1 , v cc2 at 3.3 v g007 v cc1 , v cc2 at 5 v t a = 25c t a ? free-air temperature ? c 0 2 4 6 8 10 12 14 ?55 ?35 ?15 5 25 45 65 85 105 125 t pd ? propagation delay t ime ? ns v cc1 , v cc2 at 3.3 v g004 v cc1 , v cc2 at 5 v t a ? free-air temperature ? c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ?55 ?35 ?15 5 25 45 65 85 105 125 input v oltage switching threshold ? v vit?, 3.3 v g005 vit+, 5 v vit+, 3.3 v vit?, 5 v
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 7 parameter measurement information (1) the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 ? . at the input, a 50- resistor is required to terminate the input generator signal. it is not needed in actual application. (2) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 6. switching characteristic test circuit and voltage waveforms (1) c l = 15 pf 20% includes instrumentation and fixture capacitance. figure 7. fail-safe output delay-time test circuit and voltage waveforms (1) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 8. common-mode transient immunity test circuit copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: iso7420 ISO7420M iso7421 isolation barrier c = 0.1 f 1% in v oh or v ol out v cci + C v c m v cco c = 0.1 f 1% ! gndo gndi s1 + C pass-fail criteria C output must remainstable. c l ! (1) isolation barrier v i in = 0 v v o c l (1) out v cci t fs 2.7 v v cci 0 v v ol v oh 50% fail-safe high v i v o isolation barrier v i 50 w in v o input generator (1) c l (2) out 1.4 v 10% 90% v i v o t plh t phl 1.4 v v cci 0 v 50% t r t f v oh 50% v ol
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 8 detailed description 8.1 overview the isolator in figure 9 is based on a capacitive isolation barrier technique. the i/o channel of the device consists of two internal data channels, a high-frequency channel (hf) with a bandwidth from 100 kbps up to 1 mbps, and a low-frequency channel (lf) covering the range from 100 kbps down to dc. in principle, a single- ended input signal entering the hf-channel is split into a differential signal via the inverter gate at the input. the following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. the comparator outputs drive a nor-gate flip-flop whose output feeds an output multiplexer. a decision logic (dcl) at the driving output of the flip-flop measures the durations between signal transients. if the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the dcl forces the output-multiplexer to switch from the high- to the low-frequency channel. because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (pwm) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. as the input is modulated, a low-pass filter (lpf) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 functional block diagram figure 9. conceptual block diagram of a digital capacitive isolator 14 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 8.3 feature description 8.3.1 insulation characteristics over recommended operating conditions (unless otherwise noted) parameter (1) test conditions specification unit din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm maximum working insulation voltage 566 v pk v pr input-to-output test voltage t = 1 s (100% production), partial discharge 5 pc 1062 v pk t = 60 s (qualification) v iotm transient overvoltage 4242 v pk t = 1 s (100% production) r s insulation resistance v io = 500 v at t s > 10 9 ? pollution degree 2 ul 1577 v test = v iso = 2500 v rms , t = 60 s (qualification) v iso isolation voltage per ul 2500 v rms v test = 1.2 x v iso = 3000 v rms , t = 1 s (100% production) (1) climatic classification 40/125/21 table 1. iec 60664-1 ratings table parameter test conditions specification material group ii rated mains voltage 150 v rms i ? iv installation classification rated mains voltage 300 v rms i ? iii 8.3.2 package characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit l(i01) minimum air gap (clearance) shortest terminal-to-terminal distance through air 4 mm minimum external tracking shortest terminal-to-terminal distance across the l(i02) 4 mm (creepage) package surface tracking resistance (comparative cti din en 60112 (vde 0303-11); iec 60112 > 400 v tracking index) dti distance through the insulation minimum internal gap (internal clearance) 0.014 mm v io = 500 v, t a = 25 c > 10 12 ? isolation resistance, input to r io output (1) v io = 500 v, 100 c t a max > 10 11 ? barrier capacitance, input to c io v io = 0.4 sin (2 ft), f = 1 mhz 1 pf output (1) c i input capacitance (2) v i = v cc /2 + 0.4 sin (2 ft), f = 1 mhz, v cc = 5 v 1 pf (1) all pins on each side of the barrier tied together creating a two-terminal device. (2) measured from input pin to ground. copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: iso7420 ISO7420M iso7421
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com spacer note creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 8.3.3 safety limiting values safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. parameter test conditions min typ max unit ja = 212 c/w, v i = 5.25 v, t j = 150 c, t a = 25 c 112 safety input, output, or supply i s ma current ja = 212 c/w, v i = 3.45 v, t j = 150 c, t a = 25 c 171 t s maximum safety temperature 150 c the safety-limiting constraint is the absolute-maximum junction temperature specified in the absolute maximum ratings table. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information table is that of a device installed in the jesd51-3, low-effective-thermal-conductivity test board for leaded surface-mount packages and is conservative. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. figure 10. jc thermal derating curve per vde 16 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421 case temperature ? c 0 20 40 60 80 100 120 140 160 180 0 50 100 150 200 safety limiting current ? ma g002 v cc1 , v cc2 at 3.45 v v cc1 , v cc2 at 5.25 v
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 8.3.4 regulatory information vde csa ul cqc certified according to din v vde v 0884-10 (vde v recognized under ul1577 approved under csa component certified according to 0884-10):2006-12 and component recognition acceptance notice #5a gb4943.1-2011 din en 61010-1 (vde 0411-1): program (1) 2011-07 basic insulation basic insulation per csa 60950-1- basic insulation, altitude maximum transient overvoltage, 07 and iec 60950-1 (2nd ed), 5000 m, tropical climate, 250 4242 v pk single protection, 2500 v rms v rms maximum working 390 vrms maximum working maximum working voltage, 566 voltage voltage v pk certificate number: certificate number: 40016131 master contract number: 220991 file number: e181974 cqc14001109540 (1) production tested 3000 v rms for 1 second in accordance with ul 1577. 8.4 device functional modes table 2. function table (1) input output vcci vcco ina, inb outa, outb h h pu pu l l open h (2) pd pu x h (2) x pd x undetermined (1) v cci = input-side power supply; v cco = output-side power supply; pu = powered up (v cc 3.15 v); pd = powered down (v cc 2.1 v); x = irrelevant; h = high level; l = low level (2) in fail-safe condition, output defaults to high level. 8.4.1 device i/o schematics figure 11. device i/o schematics copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: iso7420 ISO7420M iso7421 in 1 m w 500 w v cci v cci v cci out 8 w 13 w output v cco input
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information iso742x utilize single-ended ttl-logic switching technology. its supply voltage range is from 3.15 v to 5.25 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (i.e. c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application iso7421 can be used with texas instruments' mixed signal micro-controller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4-20 ma current loop. figure 12. isolated 4-20 ma current loop 9.2.1 design requirements unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the iso742x only require two external bypass capacitors to operate. 18 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421 iso7421 v cc1 v cc2
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 typical application (continued) 9.2.2 detailed design procedure figure 13. typical iso7420 and iso7421 circuit hookup 9.2.3 application curve figure 14. life expectancy vs working voltage copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: iso7420 ISO7420M iso7421 10 100 0 250 500 750 1000 v C working voltage C v iorm life expectancy C years 880 120 v at 566 v iorm 28 years g001 iso7420 12 34 87 65 ina inb outa outb v cc2 0.1 f gnd2 0.1 f v cc1 gnd1 iso7421 12 34 87 65 ina inb outa outb v cc2 0.1 f gnd2 0.1 f v cc1 gnd1
iso7420 , ISO7420M , iso7421 slls984i ? june 2009 ? revised july 2015 www.ti.com 10 power supply recommendations to ensure reliable operation at all data rates and supply voltages, a 0.1 f bypass capacitor is recommended at input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments' sn6501 . for such applications, detailed power supply design and transformer selection recommendations are available in sn6501 datasheet ( sllsea0 ). 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 15 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pf/in 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see application note digital isolator design guide , slla284 . 11.1.1 pcb material for digital circuit boards operating below 150 mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 epoxy-glass as pcb material. fr-4 (flame retardant 4) meets the requirements of underwriters laboratories ul94-v0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics. 11.2 layout example figure 15. recommended layer stack 20 submit documentation feedback copyright ? 2009 ? 2015, texas instruments incorporated product folder links: iso7420 ISO7420M iso7421 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces , pads, and vias ground plane power plane low-speed traces high-speed traces
iso7420 , ISO7420M , iso7421 www.ti.com slls984i ? june 2009 ? revised july 2015 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: ? sn6501 transformer driver for isolated power supplies , sllsea0 ? isolation glossary , slla353 ? digital isolator design guide , slla284 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 3. related links technical tools & support & parts product folder sample & buy documents software community iso7420 click here click here click here click here click here ISO7420M click here click here click here click here click here iso7421 click here click here click here click here click here iso7421m click here click here click here click here click here 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks devicenet, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: iso7420 ISO7420M iso7421
package option addendum www.ti.com 24-mar-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples iso7420d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 is7420 iso7420dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 is7420 ISO7420Md active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7420m ISO7420Mdr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 i7420m iso7421d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 is7421 iso7421dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 is7421 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 24-mar-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant iso7420dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 ISO7420Mdr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 iso7421dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 24-mar-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) iso7420dr soic d 8 2500 367.0 367.0 35.0 ISO7420Mdr soic d 8 2500 367.0 367.0 35.0 iso7421dr soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 24-mar-2015 pack materials-page 2

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